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an efficient ASIP Design Methodology | 000-277 Latest Questions and Latest Topics

Selim ZOGHLAMI*, Raphael DAVID*, Stéphane GUYETANT* and Daniel ETIEMBLE*** CEA listing, Embedded Computing Laboratory** LRI - computer Science Lab

summary :

The processors that are utilized in embedded techniques have to fulfil a group of constraints: software execution time, power consumption, chip measurement, code size and so on. in this paper, they focal point on the design of utility certain guide-set processors, and extra precisely on a good methodology for the Design space Exploration of an ASIP for the audio and speech domain. using this technique, they designed a excessive performance ASIP attaining over 13GOPS/mm2 with a 350MHz clock frequency in a low-vigor sixty five-nm TSMC expertise. The construction time was less than two man-months.

1. CONTEXT

The Design area Exploration of an ASIP (software certain guide-set Processor) will also be very complex due to the massive number of design parameters. In their design case study, they center of attention best on some key architectural aspects like the pipeline depth, the number of registers, the implementation of particular operations, the number of guidelines that can be finished concurrently and so forth. finding the superior exchange-off for the values of all these parameters isn't glaring and they want a selected design methodology to meet all necessities.

In figure 1, they present distinct tactics that can also be used to locate the superior change-off. To make the determine readable, they only use believe two design parameters P1 and P2 that can be as an instance pipeline depth and the number of guidelines which are completed concurrently.

determine 1: diverse approaches to discover the foremost values of two design parameters

(a) The exhaustive search considers all the feasible values of every parameter. Due the gigantic variety of parameters, it is infeasible to evaluate each element of the design house and compare it to the entire different ones. Heuristic search concepts should be used resulting in suboptimal answer.

(b) in order to steer clear of that an heuristic search stops the search at a local greatest, a 2d method called random sampling is offered here. It consists in selecting randomly the couples of parameters but once again there is no guaranty to converge against a suitable effect.

(c) With the guided-search approach, the fashion designer starts with a preliminary choice of two parameters, and iterates round grade by grade except discovering a suitable exchange-off. This method avoids inconsistent or conflicting values for the different parameters and represents the greatest design solution when the entry point is neatly chosen.

(d) Many other approaches may even be considered, as the use of genetic algorithms, laptop learning based mostly searches, and so on.

For their design, they use the guided search of parameters. First, they verify essentially the most essential aspects of their architecture. Then, they use a design device to quantify these distinct points and the leisure of the architecture. So what they suggest here is a design methodology based on a guided-search of parameters. The paper will proceed with the presentation of that design methodology, then the structure is exact. The outcomes and the validation outcomes of the designed processor observe. and finally, further works are delivered.

2. DESIGN METHODOLOGY

Our intention is to locate a superb exchange-off between the time-todesign and the performances of an ASIP for a particular application area.

2.1 Their benchmarks

For their case examine, they opt for the Audio and Speech necessities as a selected and mostly used domain of embedded systems. a number of audio and speech specifications with distinctive encoding concepts can be found, from lossless to lossy coding. desk 1 summarizes the set of benchmarks that they used for the Audio ASIP Design. every one of these benchmarks come from MediaBench. They cover each distinctive coding techniques and some key elements like bit-quotes and computing complexities. more particulars on audio coding recommendations are given in [1], [2], [3] and [4].

desk 1: Audio functions Benchmark

2.2 Benchmark Profiling and Analysing

The selected benchmarks have been profiled using GPROF [5], the general public GNU profiler. The outputs of the profiler deliver the call graphs and the hotspots, i.e. probably the most time consuming capabilities. For their audio-speech benchmarks, they identified 14 hotspot capabilities such as the codebook most excellent parameters filter search from the CELP (Code Excited Linear Prediction) typical or the MP3 (Mpeg-1 audio- half 3- layer 3) Modified Discrete Cosine radically change. these hotspots take over 66% of standard execution time. With these analysis of the hotspots, they cowl all audio wants. Their constrained number makes the guide analysis possible. The hotspots can even be analysed to determine the architectural features that might speed up the execution. as an instance, they can determine the register and storage wants, the statistics-course widths, and so forth. as an example, desk 2 items the variety of registers that could be necessary for an effective execution of every audio-speech hotspot. These wants had been identified from the comparison of the existence length of variables within the execution graph.

table 2: Estimated registers wants of audio-speech hotspots

we have also recognized some specific code points that may be accelerated via particular hardware elements akin to a pre-arithmetic shift. Their benchmarks also intensively use loops for which optimizing each loop conditional branches and computation conditional branches is simple.

2.3 structure Sizing

2.three.1 fundamental assumptions for the preliminary edition of the architecture

The preliminary version of the structure that they used is now offered. It uses a regular RISC (decreased guide- Set desktop) guideline set structure with 1-guide delayed branches, conditional code flags (CC flags) for conditional branches (like the SPARC ISA). The ISA (instruction- Set architecture) is implemented either with a customary 5-stage pipeline for the scalar version and the n-method superscalar or VLIW (Very lengthy instruction word) versions. Some facets in the reduction of the variety of done instructions both for the scalar or n-method versions. The variety of CC flags is one of these feature that is offered within the next part. one other fundamental characteristic is the number of directions that the hardware can execute simultaneously, i.e. the value of n for the n-approach method. It can be mentioned in a subsequent area.

2.three.2 Conditional Codes Flags Sizing

As up to now outlined, loops are general in their benchmarks and they combine a loop branch and one (or a few) computation department inside the loop. frequently, the influence of an entire loop computation is scaled on the conclusion of the loop. So they need a flag for the loop department and another one for the conditional outcome scaling. Having one or several CC flags impacts on the normal performance of the loop.

desk 3: contrast of Conditional Codes Flags Implementation

within the example shown in the desk three, enforcing two distinct CC flags saves one cycle by means of loop generation. With just one CC flag, there is not any way to refill the delay slot after the loop branch, because the CMOV instruction should follow the primary SUBCC whereas the JMP CC have to observe the 2nd example of the SUBCC. With two distinct CC flags, the CMOV guideline can be moved into the branch lengthen slot getting rid of the NOP that changed into crucial within the outdated case.

The gain can hastily grows with n-manner architectures. in this circumstance, the loop branch circumstance SUBCC1 can be evaluated within the identical cycle as one other guideline. In table 4, with a 2-means architecture, they shop a further cycle per new release.

table 4: contrast of Conditional Codes Flags Implementation for a 2-ILP architecture

The have an effect on of the variety of CC flags will also be evaluated through a metric known as ”guide utilization rate (IUR)”, it's described as the variety of positive instructions over the normal number of directions (that includes helpful and NOP directions). This guideline utilization cost can also be defined as 1−NOPpercentage. In table four, if the first M directions perfectly equipped on the structure leading to N/2 cycles and nil NOP, an contrast of that metric for both implementations ends up in:

the use of a few conditional codes flags increases the efficiency and it more effectively makes use of the capabilities of the structure. The chip enviornment cost is comparatively small and there's no situation for the instruction-set coding. most likely, the results that are shown in table 4 are in keeping with an easy 5-stage pipeline just like the MIPS-R2000 one [6]. Deeper pipelines may lead to different outcomes. as an instance, the pipeline of Alpha 21164 [7] had 2 execution degrees (EX1 and EX2): the assessment of the condition was performed throughout EX1 stage, whereas the conditional branch became finished all the way through EX2. in that case, each the guideline setting the situation and the conditional branch can also be scheduled in the same clock cycle disposing of a lot of NOP guidance in table 4. using deeper pipelines can be regarded in further works.

2.three.3 N-method architectures

The goal of the article is to latest a design methodology in response to a driving parameter well chosen. They center of attention on the number of executions to be performed concurrently because the using parameter. The main purpose to find the optimum structure that's equipped to make the most the ILP (guide degree Parallelism) that exists in the benchmarks with the minimal set of resources, i.e. the most fulfilling silicon efficiency.

We deserve to locate the most reliable triplet n-method (Nbways), guide utilization rate (Tuse) and chip area. The processor frequency and the ensuing Nbop/sec are derived from the design for every different n-way architecture.

As no compiler is obtainable for every evaluated architecture, the simplest option to find the most advantageous triplet n-method -guide utilization fee and chip enviornment is to manually agenda operations in execution kernels based on each structure. The meeting code of the recognized hotspots has been written and the corresponding execution time (in clock cycles) in accordance with the information dependencies and the instruction utilization charges had been calculated for diverse parallel architectures (2, 3, 4, 6 and 8-method architectures). They regarded two styles of information-paths : homogeneous statistics-paths have the equal processing substances whereas heterogeneous architectures have particular processing materials for every approach of the facts-route.

For their audio-speech benchmarks, on homogeneous facts-paths, the instruction utilization fee is 87% for a 2-way VLIW, seventy four% for three-manner, fifty four% for four-manner and less than 36% for wider architectures. without doubt, the hotspot loops of the audio applications haven't sufficient ILP to efficaciously exploit 6 or eight-approach architectures. The guide utilization rate on heterogeneous architectures is 87% for a 2-manner, seventy two% for three-way and 52% for 4-way architectures, as proven in determine 2.

Heterogeneous information-paths allow an important architecture area keep. at the identical time, the utilization quotes of each homogeneous and heterogeneous information-paths are somewhat similar. So, dealing with silicon effectivity because the leading metric, using parallel architectures with heterogeneous processing supplies is terribly wonderful. they will only trust heterogeneous 2, 3 and four-means architectures in the leisure of the paper.

figure 2: instruction utilization prices for n-approach architectures for audio benchmarks

The 2nd step is to select the quantity of parallelism in the structure. This step wants a prediction of the evolution of the hardware complexity when duplicating components. From a RISC processor size distribution, they estimate the chip enviornment of each parallel architectures in keeping with here hypothesis :

  • The decoder hardware complexity is ready 5% of the typical chip enviornment.
  • The fetch charge is also about 5%.
  • The chip enviornment of a register file of 32 32-bit registers is set 35%.
  • The execution gadgets are imagined to use forty% of the normal area.
  • The remaining 15% are assumed for the remaining components of the pipeline with its conversation mechanisms and pipeline registers.
  • The evolution of the hardware complexity of distinct architectural elements is additionally estimated. as an instance, they believe that the program memory access can charge is proportional to the number of fetched instructions per clock cycle. When n increases with n-method architectures, the decoder complexity raises, however many operations have mutual decoding. for that reason, they count on that the decoder area increases proportionally to the square root of the value n. Bypassing and communication mechanisms are also assumed to enhance in keeping with the identical legislation.

    because the register file and the execution devices characterize around 3/four of the normal chip enviornment, they made some particular investigations to estimate greater precisely their evolution when n increases. For the register file, a group of gate degree synthesis according to 2R/1W RF description has been performed. This look at suggests an increase of fifty% when doubling the number of RF ports, an increase of a hundred% with a 6R/3W RF and over 2.5 increase aspect for an 8R/4W RF versus the normal 2R/1W one. In desk 5, they current the hardware complexity evolution of n-approach processors incredibly to the RISC enviornment complexity.

    table 5: Hardware complexity evolution for n-way architectures with heterogeneous statistics-paths particularly to RISC processor

    Having evaluated each and every of the parameter introduced within the equation 3, they are able to consider the distinctive n-approach architectures versus the scalar implementation (i.e. bypassing the Nbop/sec that is not already standard). 4 their examine case, 2 and 3-means architectures characterize a very good alternate-off for audio-speech applications.

    2.4 construction tool

    The Synopsys Processor dressmaker [8] is an automatic design tool from the ADL (architecture Description Language) LISA 2.0. It permits a good design feedback to debug and optimize the structure. From a behavioral description of the operations, a few architectures (RISC, DSP, VLIW) can be carried out. also, an architecture debugger offers a total visibility of the parameters on the execution time : registers, contents of the different memories, guide opcodes, pipeline tiers, stalls and flushes, loop iterations, latest pipeline alerts, and the like. It makes it possible for a micro-step execution of the LISA guidelines, that is neither cycle-accurate nor instruction-correct but ”LISA-line-accurate”.

    This device is used to measurement a design standards and to hastily evaluate its have an effect on on the leading device. The construction circulation and the device points used are offered in figure three. From the starting point described in the past, this device is used all over the guided search process described in figure 1,c) of the part 1.

    figure 3: Audio Processor Design with Synopsys

    3. structure OVERVIEW

    A block diagram of the designed processor is presented in figure 4.

    This determine suggests a five pipeline stage architecture: instruction Fetch (FE), Decoding (DE), Execution (EX), reminiscence or 2nd execution stage (MEM) and RF Writeback (WB). A n-method structure with three separate records-paths. The distribution of the operators by means of information-route become acquired from the functions evaluation and their computational patterns. The guideline utilization rate estimated offers an overview of the rightness of the alternative. This distribution is given under :

  • facts-path 1 : Arithmetic and common sense Unit, Jumps and Branches, and a 16x16!32-bit Multiplier.
  • facts-route 2 : Arithmetic Unit with CC Flags version and a Shifter.
  • facts-route three : ALU, Load/store Unit, records Manipulation (including Conditional Writes).
  • All these records-paths are 32-bit signed except the multiplication. The multiplier takes 16-bit operands and explicits indications in order to help wider application (un)signed multiplications. The 16x16!32-bit multiplication is carried out within the MEM (or EX2) stage with a view to no longer prolong its essential route (i.e. processor crucial path) with the records hazard decision. The multiplier outcomes may also be used within one cycle latency. The instruction-set coding is 96-bit wide with exceptionally two source operands and one register outcomes (Opcodedestreg, src1reg, src2reg−or−imm). The 2d operand will also be a register or a right away price more often than not 14- bit wide. The Register File contains 32 32-bit registers. it's thoroughly attainable with the aid of the three records-paths: it contains 6 read and 3 Write ports. The department and jump unit isn't represented in this determine. The corresponding guidelines are applied by means of the decoder and the result is given again to the fetch stage. Branches and jumps are delayed by using one clock cycle, which capability that the lengthen slot ought to be crammed by using a helpful guide or a NOP. Like already introduced in the instance of Conditional Codes Flag Implementation, a conditional move is implemented, that either writes first or 2d operand to a register cost in accordance with the state of CC flags. This approach replaces conditional branches through conditional transfers. Its utilization raises performances because of availability of statistics-paths and freeing situation assessment ready. the load/save Unit makes it possible for facts memory access. It has four access modes : ”.W” to govern note-category records, ”.H” for signed half-word-large records, ”.UH” for same wide unsigned one and ”.B” for eight-bit one. All these access are accomplished within the MEM stage which suggests one cycle latency to use the loaded consequences.

    determine 4: architecture Overview

    four. outcomes AND VALIDATION

    four.1 structure Design

    The designed three-means VLIW ASIP VHDL RTL has been generated the use of the Synopsys Processor fashion designer device. RTL has subsequent be gate-level synthesized the usage of Design Compiler from Synopsys targeting 65-nm Low energy TSMC expertise. beneath a minimum time constraint of two.8ns, the typical chip area is set 0.07mm2 with more than forty five% dedicated to the Register File and 13% to the decoder. The validation technique consists in executing the profiled purposes and evaluating the processor performances in terms of Silicon efficiency. determine 5 summarizes the universal design move from the utility benchmarks to the ASIP performance comparison.

    determine 5: Methodology Design circulate

    First, they opt for a group of benchmarks from the utility area that they profile and analyze. Then, they seek the superior triplet variety of instructions performed in parallel - guide utilization expense and chip enviornment. For this, they verify how the meeting code of the different benchmark kernels execute on each and every n-manner architecture and they consider the execution time and the guide utilisation expense. Third, they use a design device to measurement an effective processor. They iterate the process until they meet their necessities. eventually, they validate the designed processor with a gate-level synthesis and they execute the studied hotspots kernels.

    As no compiler turned into available, the assembly code of three hotspots became manually-written and optimized to validate the ASIP structure. The hotspots of the profiled functions were finished on the processor resulting in an instruction utilization expense of 86%. They observe that most effective three of the 14 hotspot features were manually-written to consider their processor. They handiest represents about 20% of the common execution time. The Silicon effectivity of a processor is given through:

    The silicon effectivity of the designed ASIP is then:

    The designed three-way processor promises about 13GOPS/mm2. The development lasted a few months. Its clock pace is about 357MHz and it executes successfully GSM (world gadget for cellular communications), CELP, ADPCM (Adaptive Differential Pulse Code Modulation) and MP3 functions.

    four.2 performance evaluation

    The Synopsys Processor dressmaker allows a quick technology of alternative Audio ASIP models according to the designed one. The purpose to the introduced design methodology is to demonstrate that the design parameters were accurately sized. A small modification of one of them results in completely diverse effects. In an instance earlier than, they showed the impact of enforcing two diverse conditional codes flags. Now they accept as true with the have an effect on of smaller directions.

    Few modifications are performed to the ADL description to design 2-way VLIW and RISC implementations. Evaluating their performance with the audio benchmarks results in different results in silicon efficiency as presented in figure 6.

    determine 6: Normalized silicon efficiencies finished via distinctive n-way processors

    For the three evaluated hotspot features, they certainly observe that n-method architectures are better than scalar ones. at first of the analyze, taking simplest these three hotspots, three-means architecture become 0.seventy eight instances less efficient than the 2-way one in terms on Silicon efficiency. however for all the hostpots, both models had been rather identical. The outcomes given within the figure 6 after implementation refer only to the execution of the three hotspots. So if they anticipate that the evolution from the preliminary outcomes to the effects after implementation may be the identical for the entire hotspot services, then they predict that the 3-manner processor might be 1.23 instances more advantageous than the 2-means one and even more versus the scalar implementation.

    SPARC v8 is an guideline-set for RISC processors including load/keep, arithmetic, common sense and shift directions and all of the imperative stuff for executing a big amount of purposes. They select the Leon3 implementation of the SPARC v8 ISA to be their referent for the ASIP efficiency finished. The Leon3 has a seven stage pipeline with a Harvard structure (with separated program and facts memories). It includes a hardware multiplier/divider and a three-port Register File. The special register file consists of 32 registers organized in windows. The three validation features are executed on it and its RTL implementation is gate stage synthesized with the same Low-energy TSMC library. The universal design size is ready 0.035mm2 with a clock pace of 357MHz. In table 6 they evaluate both the consequences of the designed three-way ASIP and the outcomes of the Leon3 processor executing the audio functions. With the described design methodology, the audio-speech 3-method ASIP is set 70% more efficient than the Leon3 processor.

    table 6: Audio ASIP vs Leon3 Silicon Efficiencies

    5. CONCLUSION AND FUTURE WORK

    The utilized methodology allowed a quick Design space Exploration and an effective sizing of the important thing parameters. Their methodology has a couple of boundaries:

  • Manually assembly coding an entire benchmark can’t be finished to opt for the correct architecture sizing. in the audio illustration, they modeled over 66% of the set of their benchmarks. This leads us to the alternative of a three-method structure, however they have no guaranty that the last 34% would no longer modify this alternative.
  • Predicting the evolution of complexity can infrequently be executed if we're confronted to complex equipment designs with hierarchical memories and complicated community connections.
  • The designed VLIW ASIP changed into very effective when it comes to efficiency. however its Silicon efficiency turned into badly decreased through its chip area. They seen that the Register File took over 45% of the overall enviornment. In future works, they will focus on decreasing the ordinary system silicon can charge.

    REFERENCES

    [1] Karlheinz Brandenburg, Oliver Kunz, and Akihiko Sugiyama. Mpeg-4 herbal audio coding. sign Processing: picture conversation, 15:423–444, 2000.

    [2] M. Budagavi and J.D. Gibson. Speech coding in cell radio communications. lawsuits of the IEEE, 86(7):1402–1412, July 1998.

    [3] Andres Vega Garcia. M´ecanismes de controle pour la transmission de l’audio sur l’internet. PhD thesis, exceptional- Sophia Antipolis tuition, October 1996.

    [4] A.S. Spanias. Speech coding: a tutorial review. lawsuits of the IEEE, eighty two(10):1541–1582, October 1994.

    [5] http://www.ibm.com/developerworks/linux/library/lgnuprof.html?ca=dgr-lnxw02gnuprofiler.

    [6] N. Pinckney, T. Barr, M. Dayringer, M. McKnett, Nan Jiang, C. Nygaard, D. funds Harris, J. Stanley, and B. Phillips. A mips r2000 implementation. pages 102– 107, June 2008.

    [7] P. Bannon and J. Keller. inner architecture of alpha 21164 microprocessor. In Compcon ’95.’applied sciences for the information Superhighway’, Digest of Papers., pages seventy nine–87, Mar 1995.

    [8] Karl V. Rompaey, Diederik Verkest, Ivo Bolsens, and Hugo D. Man. Coware - a design environment for heterogeneous hardware/software systems. EURO-DAC, pages 252–257, 1996.


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