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developing a Reusable IP Platform within a equipment-on-Chip Design Framework centered towards an educational R&D ambiance | P2065-036 Practice Questions and braindumps

via Brendan Mullane and Ciaran MacNamee,Circuits and device analysis Centre (CSRC),school of Limerick, Limerick, eire

summary:

A key challenge facing the semiconductor industry is to combine intellectual Property (IP) from a number of sources instantly and successfully. Design instances are normally pressurized by using time to market necessities and extending complexity. Industrial practices for developing equipment-on-Chip (SoC) IP have advanced beneath these pressures, but making use of these practices in an academic ambiance gifts additional challenges. The conception for constructing a framework for producing IP was according to this reuse revolution and the advantages it brings to R&D. The potential to design high excellent IP and to enable work practices for reuse methodology helps to achieve working SoCs in a well timed and productive manner. This paper describes a methodology for enforcing IP reuse practices suitable to an tutorial atmosphere.

1. Introduction

quite a lot of factors are essential for productive IP use, flexibility of integration, more advantageous ease-of-use, minimized charge, and respectable work practices for setting up IP. This paper is in accordance with exact work developing an ASIC the use of 0.35ìm system expertise. The architecture in this IC is akin to SoC designs that use an 8-bit CPU and linked peripherals. it's proven that the framework for IP development centered all through this task can make certain a success deployment of each existing and new designs in future tasks.

The latest trend in SoC design is to utilize current IP as a good deal as viable. IP within the form of CPUs, DSPs and controllers, are being reused in new IC tasks at semiconductor techniques design properties. Engineering groups now design chips with millions of gates in below a year. only recently, such productiveness would were not possible, even unthinkable with out hardware IP reuse. Most tutorial environments don't have the materials and infrastructure to permit such engineering capability, youngsters the underlying concepts of reuse may also be applied to enable more effective IP era and expertise retention for advantageous R&D.

This paper introduces a collection of instructions and a strategy used to make certain a consistent method to designing IP and to permit for reuse of these modules in future projects. the first stage changed into to investigate foremost industrial practice. Work describing the ASIC development cycle and its affect on IP technology became performed. a collection of requirements for making certain IP high-quality and ease of integration was also organized. A key aim became to make certain skills can be retained within the university centre to take into consideration anticipated graduate turnover.

2. IP Reuse Framework in CSRC

A evaluate of the typical issues in design use and reuse become initiated [1]. quite a few IP requisites were reviewed and these included Freescale’s Semiconductor Reuse average [2], VSI Alliance’s set of requisites for constructing SoCs [3] and OpenMORE [4]. IP reuse might in no way have took place without specifications or devoid of the underlying infrastructure [5]. Design and verification reuse, a truth of lifestyles these days for most SoC designs, ensures the productivity gap is kept manageable[6]. Design reuse regarded an easy conception that may also be comfortably adopted, has endured to be troublesome in practice. problems exist in getting engineers to have faith that reusable IP will work anytime it's used in an IC. presenting IP aid capabilities and adoption of a proper verification process develops this believe.

2.1 SoC architecture and Infrastructure

The aim of this mission become to set up a design methodology for producing IP. The methodology involved architectural decisions and choice of design-flows for IP construction accompanied by means of the prerequisite IC design tools. task criteria such because the SoC architecture, third-celebration core use, in-residence IP building and the system bus interface had been all considered before the IC structure changed into concluded and the peripheral integration changed into performed. The fundamental SoC architectural diagram is shown in figure 1 and the complete chip turned into taken through verification and the again-conclusion tiers of synthesis, design, static timing evaluation and final design rule checking.

figure 1: SoC Design architecture

the following key selections had been made relating to the IP assist constitution.

2.1.1 Peripheral Bus Interface

The selection of a common SoC device bus for connecting the CPU to the equipment peripherals was important to the pursuits of this venture. the use of a standardized bus architecture is fundamental to establishing reusable IP. quite a few bus specifications were investigated for the wants of the CSRC IC tasks. The 8051 CPU changed into used in this design and despite the fact the internal special feature Register (SFR) bus become regarded, the authors wished to employ a typical bus design to be reused in other IC implementations.

many of the fundamental IC and IP groups base their IP portfolio building round a single SoC bus architecture. Semiconductor agencies akin to ARM and LSI logic use the open source AMBATM [7] bus commonplace. IBM uses its personal proprietary CoreConnectTM [8] bus common. The OpenCores initiative makes use of the WishboneTM [9] described bus interface. The authors observed that the AMBA bus structure turned into smartly supported amongst the IP seller neighborhood. This extensive acceptance arises from the supply of an open bus usual it really is license free and well confirmed in current SoC designs. purchasers have a high diploma of self assurance identifying IP it really is considered dealer impartial. moreover, the AMBA bus is well supported by way of EDA companies providing verification aid. The AMBA bus become chosen as the bus interface for CSRC SoC projects for these motives.

The AMBA bus permits partitioning for modular designs[10]. Its methodology for embedded processor design encourages each a modular and first time appropriate equipment design. It additionally hastens product migration by way of assisting module reuse. In specific, the AMBA APB bus specifies a flexible interface and small overhead aid for low bandwidth peripherals. The IP design the usage of the AMBA interface is made more convenient by using partitioning the high-end and low-conclusion contraptions in the equipment and helps energy efficient designs. all of the peripherals during this design used the AMBA - superior Peripheral Bus (APB) as the standardized interface. The CPU as a single bus master become interfaced to all of the peripherals by way of an in-condo designed AMBA bridge interface.

The advantages of using a common bus interface for core building are smartly documented [1, 10, 11]. A demo AMBA APB register module, shown in determine 2, changed into beneficial for demonstrating the preferred interface design to postgraduates. The RTL code for this module helped the team to have in mind the concepts of first rate coding observe to consist of parameterization and Verified the use of revision handle for code adjustments and malicious program fixes. the entire IP developed during this IC project can be reused in another AMBA primarily based SoC purposes and this aids future product and platform construction

figure 2: demo APB module

2.1.2 third party Core Licensing

another giant assignment changed into to designate an appropriate microcontroller for the venture. The IP group became approached in regards to licensing of the CPU and debug cores. there were a number of facets to licensing IP cores from an tutorial viewpoint. It become simple to be certain a licensing arrangement become made the usage of a non-commercial analysis- licensing mannequin. Many carriers have been only prepared to license their cores in line with a full industrial arrangement and the prices quoted were past an academic research funds. Some companies had been willing to consider a decreased non-commercial license price with the re-introduction of full costs supplied the IC proceeds to business utility. different IP companies restrained their set of deliverables to FPGA netlist implementation best. This restrained their choice of 3rd celebration CPU and debug cores. fortunately, some IP businesses had experience dealing with educational situations and were organized to release IP deliverables and help for non-industrial research exercise at a reduced cost. The leading author become able to perform a survey of correct cores and got here to an contract for the third party IP obligatory for the SoC task.

2.1.3 Design Flows

The ASIC design flow and digital Design Automation (EDA) tool selection is an important component of an efficient IP framework. The choice of tools ought to complement the design flows and aid reusability of IP. The centre accesses tool units provided as educational programmes from the semiconductor EDA businesses. The CSRC also has entry to familiar EDA equipment by way of the Europractice[12] software service scheme. Their FPGA and Digital design flows were drawn up across the availability of these tools and to plot the SoC IP development and integration. These flows had been effective in identifying the distinctive degrees concerned in the building of IP and SoC designs. apart from the digital design flow, a circulate for FPGA prototyping become additionally delivered. The FPGA building enables for an inexpensive design validation platform and provides confidence by using making certain correct conduct before ultimate tape-out.

2.1.3.1 Digital IC Design stream

The digital design follows the classic ASIC implementation route. a couple of semiconductor enterprise websites and technical paper searches published the regular design flow that exists for digital ASIC design [13], [14].

determine 3: Digital IC design circulate

The design flow and equipment preference as drawn up in determine three have been tailored to device availability and the alternative of IC methods supplied with the aid of Europractice.

2.1.3.2 FPGA Design flow

The FPGA circulate in determine 4 is awfully akin to the digital IC design move, however the design tools to enforce and application a FPGA design are diverse. The mission used the Xilinx design kits and tools made available via the Xilinx university Programme. They used Xilinx Spartan 2 and 3 boards to put into effect the digital design facets. The Xilinx ISE webpack is a collection of equipment that takes Verilog RTL code and runs it through synthesis, real design to machine configuration. The final bit file can then be downloaded to program the FPGA equipment to examine the functional habits of the digital design. FPGA verification ideas and their magnitude in design validation and reuse are discussed later.

figure 4: FPGA Design stream

2.2 CAD Infrastructure

The CAD infrastructure become improved to carry out SoC building inside the centre. The long-established structure blanketed three low-grade UNIX servers for working the IC design equipment and maintaining venture records. A plan become initiated to Excellerate the IT hardware needs. each of the consumer PCs were put in with VMware Linux, allowing clients to retain their home windows OS however extra importantly each computing device could use its personal CPU processing power with Linux to bring more desirable performance. Two excessive vigor Linux mainframes, received for holding the project databases have been also utilized as license servers for the supported EDA equipment. the brand new set-up gives the efficiency necessities to carry out IC R&D in the CSRC centre.

a different step was picking out the EDA equipment essential for IP development. tools for verification and ensuring quality of RTL code were now not in vicinity. youngsters the usage of their Europractice membership, the centre had entry to usual EDA tools at a reduced charge. equipment akin to ModelSim for RTL verification and Leda for RTL analysis have been got. The latest version of Design Compiler become additionally upgraded in keeping with trade necessities.

3. Design Methodology and IP reuse Implementation

software of reuse can pay off when it comes to development charge and time-to-market. This area summarizes the construction milestones for a typical IP design. Defining the move and associated design reviews helps certain a repeatable, excessive best, and reusable block of peripheral IP. an extra benefit of a documented circulate is that other design corporations can use this technique to strengthen IP in an identical way; ensuring IP is consistent in its implementation, integration stream, deliverables, and universal first-class.

3.1 construction Milestones

IP/SoC design milestones are essential to the start of working silicon and attaining a ‘right first time’ coverage. These milestones are markers placed down all over the construction part to control and measure the design undertaking and progress. These markers indicate stories occurring throughout the essential ranges of the design phase from beginning to conclusion. Milestones take vicinity at the natural development of the assignment. determine 5 and table 1 describe the signal-off milestones to consist of all essential design experiences.

figure 5: IP development Milestones

desk 1: IP building levels

degreeReview Description FSR useful Spec review purposeful specification is comprehensive, details on effort estimation, work breakdown constitution and schedule. DSR Design beginning evaluation Design birth, practicing, RTL coding & synthesis checklistTPR look at various Plan evaluate complete specification of verification environment, check instances, bus-models, transactors. RCR RTL Code overview RTL computer virus fixes identified via exhaustive verification & RTL Lint/code checking TLR Trial design overview establish floorplan and function P&R. Floorplan in accordance with module connectivity, resolve congestion and timing –examine clocking FVR last Verification assessment high priority trying out accomplished. conventional bugs within the RTL are fastened. insurance analyzed. Low precedence trying out good enough. FDR closing Design evaluate review integrity exams (DRC, LVS) STA, check Vectors and remaining gate-level verification with comprehensive layout timing.

3.2 challenge Database structure

A standardized directory constitution is vital for IP reusability. an effective and easy to make use of database constitution ensures compatibility and consistency of peripheral design. IP construction involves specification, coding and verification as key design levels. in consequence, many aid file formats are required. IP maintenance is also a key conception in IP reuse. The ability to log and keep track of design changes is vital to the common pleasant of the design. determine 6 suggests the CSRC directory structure to guide the IP construction degrees.

determine 6: usual CSRC listing Database

three.3. Reuse guidelines

3.3.1 Specification reports

The design studies are enormous when it comes to producing a framework for IP construction and reuse. These reports support documentation and ensure respectable design practices.

three.three.2 functional Specification

This document provides an in depth useful description of the module and is written ahead of the IP building. The FSR evaluation takes vicinity to be certain all features of the peripheral functionality are lined. The specification should be used to birth the design and RTL coding. The functional specification must be up to date for this reason with any additional points requirements. The CSRC uses a draft template doc as a suggestion for producing useful block and IC design necessities.

three.three.3 RTL Coding and analysis

RTL development includes coding the peripheral in a hardware description language equivalent to Verilog or VHDL. Verilog RTL was used and a set of coding instructions for the IP technology become issued. This set of coding concepts ensures consistency, coding style great and gives for more suitable preservation. The RCR is a high stage evaluation of the RTL code to be sure it is stylistically correct and maintainable. The intent is to double-investigate the code first-rate. The basis for this assessment is the RCR checklist. RTL evaluation is carried out the usage of Leda for crosschecking RTL code suggestions in opposition t the Reuse Methodology manual (RMM). initial FPGA/IC synthesis can also be used to spotlight any RTL issues in regards to synthesis.

three.three.four Revision manage

Revision control is crucial to the thought of design reuse and ensures important tips isn't lost all through the design phase. Revision handle and file administration is certainly crucial during RTL coding as any code lost right through this stage can critically have an effect on the universal design timeline. To help control data, engineers use source control administration programs. These are customarily bundled with the Linux operating techniques or accessible from GNU (RCS, CVS, Subversion). These code administration programs provide a complete background of every file as separate types.

three.three.5 computer virus maintenance

dealing with bugs is a vital consideration for any design framework. it's general to discover useful irregularities in the design and their occurrence does not reflect the abilities of hardware designers. as soon as an issue is recognized, it needs to be resolved. All design groups want a method for monitoring concerns and ensuring their decision. The authors proposed keeping a computer virus record for any design related concerns.

three.4 Verification and Validation atmosphere

The verification part is crucial to supplying first time working silicon. Their verification methodology makes use of a twin music approach. Verification happens at the module stage and additionally at the SoC gadget level. The Module Verification atmosphere (MVE) functionally validates the core and ensures all design features have been comprehensively established. The SoC Verification environment (SVE) checks the cores’ habits on the equipment stage and in particular checks the connectivity between the core interfaces. An FPGA/ASIC design verification approach turned into used to validate the mission on the system SoC degree.

three.four.1 Module Verification ambiance (MVE)

an important part of the MVE turned into the generation of the APB Bus functional model (BFM) to generate the functional conduct of the equipment bus. all of the peripherals were according to this standardized bus structure and this enabled using a customary model to examine the bus interface and registers contained in the peripherals. This model additional offered an easy to make use of check ambiance. The diagram in determine 7 illustrates this. The BFM utilized Verilog projects for examine/write accesses, including wait state manage and turned into reused in all of the peripheral verify environments. The BFM turned into constructive for working checks to achieve confidence within the functional habits and for targeting excessive code coverage.

figure 7: APB Bus useful model

3.four.2 SoC Verification ambiance (SVE)

The SVE consisted of a separate however equivalent check answer for FPGA prototyping and the ASIC equipment stage verification. The FPGA solution became constructive for mapping the finished SoC RTL code to consist of the CPU, debugger and the entire peripherals onto a FPGA. determine 8 illustrates the basic architecture applied onto the FPGA machine.

figure eight: FPGA Prototype Validation

The CPU and different main peripherals are connected together as a single platform and tests had been developed in R8051 CPU core software code to function the peripheral tests. The ASIC verification atmosphere is akin to the FPGA check mattress, apart from in this case all checks had been run using RTL and technique specific gate-degree stimulations. every of the peripheral firmware tests developed for the FPGA prototyping have been reused at ASIC device level.

4. consequences and Conclusions

The mission objective was to put in force a SoC design framework for the birth of reusable IP. The chosen common gadget bus aided the construction of plug and play peripherals that can be reused in many other SoC purposes. The building of the 8051 CPU exterior data bus to equipment bus-bridge supplied for a standardized interface and simplified the peripheral development.

The design flows of Figures 4 and 5 were followed to ensure a consistent design method for the building and equivalent support for industry normal EDA equipment. The directory constitution as explained in part three.2 became additionally important for associating files with each and every stage of the IC building and conserving a neatly-managed database. each and every of the implemented IP blocks follows this widely wide-spread database structure and this ensures reusability going ahead. Design reports ensured confidence and first-rate of the IP block design. The Verilog code was reviewed to be certain revision control and RTL coding instructions had been adhered to. a similar overview turned into performed to make certain the verification environments at module and system degree were acceptable to test the functionality of these designs. The RTL changed into validated on a FPGA machine and assessments have been conducted at the gadget level to test the peripherals related to the 8051 CPU.

The IP framework as mentioned during this paper is correct for implementation in an tutorial centre wishing to perform a reusable IP programme. this system and reuse concepts are commonplace in industry, however because of funding and aid constraints, might also no longer all the time be convenient to install in an tutorial ambiance. This paper discusses the implementation of IP construction for lessen bandwidth peripherals; having said that the underlying concepts of IP use and reuse are the identical.

4.1 academic Centre Specifics

group of workers necessities for research are eventually resourced from graduates pursing MEng and PhD levels. in the CSRC, staff and academic researchers are answerable for leading tasks and mentoring college students. The graduates want potential construction to deliver them up to velocity and having a structured development methodology permits deliverables to be met in a timely style. The benefits of IP skills retention turned into another excuse for introducing the IP development framework, as work generated on initiatives conducted during the past would have been tricky to progress as soon as postgraduates had completed their analysis levels. This changed into a vital situation to get to the bottom of, as valuable task work performed in the past may additionally were unnecessarily misplaced.

4.2. Future options

The cores can be additional greater by featuring a device C or C mannequin as part of the developmental levels to extra the stage of abstraction and to velocity up design verification and application development.

SystemVerilog is a hardware design and verification language with superior features supposed to help users enhance reusable, transaction-level, coverage-driven testbenches. suggestions comparable to fact based mostly Verification (ABV) may well be utilized to the bus protocol to video display pin endeavor and the software of coverage-pushed tests add self belief in working silicon and supply an exhaustive trying out environment. These facets introduce concepts of verification reuse.

Design for check (DfT) is frequently excluded from the design circulate in an tutorial ambiance. DfT is a extremely vital function essential for IP reuse. The IEEE 1500 normal for Embedded Core verify (SECT) specifies a core wrapper design to accommodate DfT aspects. This IEEE 1500 compliant wrapper design could deliver a effective extension to the present IP building tiers.

5. Acknowledgements

The authors acknowledge the aid of the Circuits and systems research Centre (CSRC) within the electronic and computer Engineering (ECE) Dept. at the school of Limerick.

6. References

[1] Australian Microelectronics network, "IP design and Re-use," Jun, 2005.

[2] Freescale Semiconductor, "Semiconductor Reuse normal v3.2," Feb, 2005.

[3] VSIA Alliance, "VSIA structure document v1.0," Mar, 1997.

[4] P. Bricard, Jean-Pierre Gukguen, "applying the OpenMORE evaluation application for IP Cores," in ISQED 2000: Synopsys, Mentor portraits, March, 2000.

[5] J. Shandle, G. Martin, "Making embedded software reusable for SoCs," EETimes, Jan, 2002.

[6] J. Bergeron, "Writing Testbenches - useful Verificaton of HDL models", Kluwer educational Publishers, 2003.

[7] ARM, "AMBA™ Specification (Rev 2.0)," ARM LTD, might also 1999.

[8] IBM. CoreConnect Bus. architecture, "http://www-03.ibm.com/chips/products/coreconnect/."

[9] R. Herveille, "WISHBONE gadget-on-Chip (SoC) Interconnection structure for moveable IP Cores," OpenCores corporation, Sep, 2002.

[10] D. Flynn, "AMBA: Enabling Reusable On-Chip Designs," IEEE Micro, vol. 17, 1997.

[11] M. Kaskowitz, "flexible, requirements-based IP key," EETimes, Dec, 2002.

[12] Europractice, "http://www.msc.rl.ac.uk/europractice,"

[13] QualCore good judgment, "QualCore SoC flow."

[14] V. P. Nelson, "VLSI/FPGA Design and examine CAD tool movement in Mentor portraits," Feb 15, 2006.




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References :


https://arfansaleemfan.blogspot.com/2020/08/p2065-036-ibm-i2-ibase-support-mastery.html
https://www.4shared.com/office/l4EWGIHliq/IBM-i2-iBase-Support-Mastery-T.html
https://sites.google.com/view/killeams-p2065-036-examdumps
http://ge.tt/8FsR1k73
https://www.4shared.com/video/tsleZzN9ea/IBM-i2-iBase-Support-Mastery-T.html
https://ello.co/killexamz/post/kilkrbbahvtar92nhkkbpw
https://youtu.be/p1-3LYLYmgI
https://justpaste.it/P2065-036
https://www.clipsharelive.com/video/7598/p2065-036-ibm-i2-ibase-support-mastery-test-v1-question-bank-with-real-questions-by-killexams-com
https://www.instapaper.com/read/1411071878
https://drp.mk/i/1zpqSGVLJW
http://killexams.decksrusct.com/blog/certification-exam-dumps/p2065-036-ibm-i2-ibase-support-mastery-test-v1-2021-updated-dumps-by-killexams-com/
https://spaces.hightail.com/space/v47qz1ixkg/files/fi-c8fa9eb6-e6ac-47a1-aa03-fe0443ebdaee/fv-a4b7aded-b3e3-4b70-85c1-c3e942fabfe2/IBM-SPSS-Predictive-Analytics-Sales-Mastery-v1-(M2020-229).pdf#pageThumbnail-1
https://files.fm/f/hpgqpa2sp



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